Quantum computing’s threat to today’s cryptography has been evident for some time. More than half of surveyed experts expect a cryptographically relevant quantum computer within 15 years, and as many as 49% say within 10.
The timeline that matters more, however, is the one set by regulators. The EU Cyber Resilience Act’s reporting obligations began September 11, 2026, with full requirements following in December 2027. NSA’s CNSA 2.0 requirements for new national security system acquisitions begin in January 2027.
Most compliance planning has centered on software that encrypts data in transit and at rest. That overlooks a system’s first line of defense: the hardware root of trust (HRoT) that authenticates firmware and anchors trust for everything above it.
Why Hardware Is the Gap
Traditional HRoT options are fixed-function, with device IDs and firmware signatures locked in at design time. That stability is what makes them trustworthy, but it also locks in algorithm choices. When those algorithms age out, designers must replace the component or layer software on top. Because software updates are far easier than hardware changes, many systems pair modern software with legacy hardware. That works only as long as the underlying algorithms hold.
Quantum computing ends that arrangement. NIST has finalized ML-KEM (FIPS 203), ML-DSA (FIPS 204), and SLH-DSA (FIPS 205), and specifies LMS and XMSS (SP 800-208) for firmware signing. Yet most traditional HRoT options, including MCUs and secure-boot SoCs, rely solely on RSA and ECC, which a sufficiently powerful quantum computer can break. No software layer can fix a foundation that cannot be trusted.
Decision-makers are left in a difficult position. Existing devices are no longer adequate, and quantum capabilities will keep changing quickly and unpredictably. They need an approach that addresses today’s threats while remaining adaptable to tomorrow’s requirements.
Supporting a Crypto-Agile Future
The answer is cryptographically agile, hardware-level protection. Crypto-agility, the ability to update cryptographic algorithms in the field without replacing hardware, offers a path to protection without sending systems back to square one.
Crypto-agile PQC systems counter the perception that an effective HRoT must be completely static. They preserve the fixed security elements that matter while adding flexibility where it is needed, through a combination of features:
- Secure field-update paths that let hardware adjust to changing needs after deployment
- Anti-rollback protections that prevent forced downgrades
- Dual protection that allows classical and PQC algorithms to run side by side during the transition
- Quick startup that reduces boot-sequence exposure
Adaptable hardware such as Field Programmable Gate Arrays (FPGAs) makes crypto-agility accessible in a unified hardware package. A single FPGA can serve as both the HRoT and the system control layer, handling boot, power sequencing, and monitoring in one place, while reconfigurable logic allows security functions to be updated after deployment. Low-power, always-on operation, deterministic low-latency response, parallel processing for multiple simultaneous key operations, and high I/O capacity add to their value in secure-by-design systems, with or without PQC considerations.
Specialized FPGAs like the Lattice Mach™-N2 family are built for PQC-ready operation. Mach-N2 offers logic densities of up to 220k cells and boots in under 30 milliseconds, closing the firmware-boot gap that leaves systems exposed. It supports a full CNSA 2.0-compliant PQC suite (ML-DSA, LMS, and XMSS for authentication, ML-KEM for key exchange) alongside AES-256-GCM, ECC521, and RSA4096 for backward compatibility. Field-updatable algorithms let designers and operators adapt as requirements change, and PUF-derived device identity with DICE and SPDM support extends trust across the platform and supply chain.
The root of trust is only one layer. Protecting platform firmware across its lifecycle also requires detection, recovery, and attestation, and these capabilities need to be post-quantum ready as well. Platform Firmware Resilience (PFR) aligned to NIST SP 800-193 provides protection, detection, and recovery, while SPDM 1.4 attestation extends trust across the devices in a system. Solutions such as the Lattice Sentry™ solution stack pair PQC-enabled PFR and attestation with a crypto-agile hardware root of trust, giving teams a practical path to PQC-ready operation.
Building for Unknowns
PQC preparedness will take years and will evolve as attackers and protections adapt to one another. The hardware designers choose today must meet requirements that have not yet been written. The only certainty is that the unknown is coming, so the right foundation is one built to change as quickly as the quantum landscape.
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